(1) Field of the Invention
The present invention relates to a technique for controlling a circuit group that includes a processor circuit or the like, and in particular, relates to a circuit group control system that causes circuits in a circuit group to operate in accordance with a command issued from a processor.
(2) Description of the Related Art
A system is known in which a certain processor (hereinafter referred to as a master processor) gives a commission of executing a command to a circuit operating as another processor (hereinafter referred to as a slave processor), a DMA controller circuit or the like. Hereinafter, such circuits as the slave processor and the DMA controller which are given a commission of executing a command are referred to as slave hardware units.
This system enables the master processor and the slave hardware to operate concurrently, resulting in faster data processing by a program that the master processor decodes and executes.
Meanwhile, there is a case where a certain job is completed only when a plurality of commands respectively corresponding to a plurality of slave hardware units are executed in a certain order.
In executing such a job, it is effective that the master processor gives a commission of executing a plurality of commands in a certain order to a group of slave hardware units collectively as follows: (a) the master processor issues a command sequence that is a plurality of commands arranged in a certain order to be executed respectively by corresponding slave hardware units, to a control unit for controlling the group of slave hardware units,; and (b) the control unit, upon receiving the issued command sequence, decodes the plurality of commands one by one in the order, identifies the slave hardware units that correspond to the decoded commands, and causes the slave hardware units to operate in accordance with the decoded commands. This method is effective in that it reduces the processing overhead of the master processor in sending or receiving commands, and increases the speed of the data processing.
A command sequence is composed of, for example, a command A instructing the DMA controller to transfer a set of data of approximately several hundred kilo bytes from a main memory to a local memory, a command B instructing the slave processor to perform a calculation based on the set of data stored in the local memory and store a set of data as the calculation results into the local memory, and a command C instructing the DMA controller to transfer the set of data as the calculation results from the local memory to the main memory, where these commands are arranged in this order to be executed in the same order.
Upon receiving the command sequence as an example from the master processor, the control unit controlling the group of slave hardware units first causes the DMA controller to execute a process A that corresponds to the command A, then after completion of the process A, causes the slave processor to execute a process B that corresponds to the command B, then after completion of the process B, causes the DMA controller to execute a process C that corresponds to the command C.
Here, there are cases where the master processor needs to cause a slave hardware unit group to execute a plurality of command sequences as necessary when, for example, the data processing of the target job can be treated as a plurality of tasks.
In such cases, the master processor issues to the control unit two or more command sequences that instruct a plurality of slave hardware units to operate in conjunction with each other. Generally, a normal control unit for controlling a group of slave hardware units executes the command sequences one by one by causing slave hardware units to execute corresponding commands constituting each command sequence one by one, in the order of arrangement.
However, in this method, the slave hardware units are not effectively used. This is because according to the method, commands constituting a command sequences are executed one by one by corresponding slave hardware units, and this process is repeated for each command sequence, and therefore only one slave hardware unit among those in a group is operable at a time.